Clock Generators for Soc Processors

Current literature is filled with textbooks and research papers describing frequency synthesizers from a front-end wireless transceiver perspective. The emphasis has historically been on evaluating the frequency synthesizer's performance in the frequency domain, i.e. in terms of phase noise and spurious signals. As microprocessor frequency surges, the need to understand digital requirements for low-jitter and the design of low-jitter frequency synthesizers and clock generators becomes increasingly important.  Clock Generators for SOC Processors is dedicated to the time-domain (i.e. jitter) design and analysis of frequency sythesizers and clock generators for microprocessor applications.  In the past, such explanations have been scattered, and have not, to this date, been gathered into one comprehensive textbook. Clock Generators for SOC Processors also focuses on the CMOS IC implementation of such synthesizers. An entire chapter is dedicated to low-voltage mixed-signal integrated circuit design in deep submicron CMOS technologies. Subsequent chapters discuss the design and analysis of the most common frequency synthesizer, the phase-locked loop (PLL), as well as state-of-the-art innovative architectures suitable for system-on-a-chip (SOC) processors. Design for Testability (DFT) is also discussed in the context of frequency synthesizers in SOC processors. The book concludes by discussing some of the most common issues that arise in clock interfacing, clock distribution, and accurate delay generation through delay-locked loops (DLLs) as they apply to SOC processors. Such issues mainly arise from having to communicate data and clock signals across multiple clock and power domains. Clock Generators for SOC Processors provides numerous real world applications, as well as practical rules-of-thumb for modern designers to use at the system, architectural, and circuit level.