DESIGN OF 4x4 BIT SRAM USING VHDL

Memory arrays are an essential building block in any digital system. The aspects of designing an SRAM are very vital to designing other digital circuits as well. The majority of space taken in an integrated circuit is the memory. SRAM design consists of key considerations, such as increased speed and reduced layout area. The hope for this project was to be able to create an efficient and compact SRAM. Due to time limitations, the goal was to create a working SRAM design and to learn how the SRAM functions. Design choices were made and justified appropriately. RAM has become a major component in many VLSI Chips due to their large storage density and small access time. SRAM has become the topic of substantial research due to the rapid development for low power, low voltage memory design during recent years due to increase demand for notebooks, laptops, IC memory cards and hand held communication devices. SRAMs are widely used for mobile applications as both on chip and off c, because of their ease of use and low standby leakage .The main objective of this paper is evaluating performance in terms of Power consumption, delay .

Mr.Amit Bhattacharyya received M.Sc in Electronic Science and M.Tech in Radio Physics & Electronics degrees in 2006 and 2008 respectively from The University of Calcutta, West Bengal, India. Presently, he is acting as Assistant Professor of Electronics & Communication Engineering Department of Haldia Institute of Technology, Haldia, West Bengal. He is working towards his Ph.D. degree. His main areas of interest include Power Electronics, Control Systems and Microprocessor based system Design. He is a member of IAENG, HONG KONG (Membership Number: 145430)