Designing TSVs for 3D Integrated Circuits

Introduces readers to challenges and best practices in designing TSVs for 3D integrated circuitsDiscusses how TSVs induce noise affecting neighboring devices, provides a methodology to evaluate noise and evaluates several techniques to eliminate and reduce TSV noiseInvestigates the impact of TSV size and granularity on power delivery for 3D ICs within a novel framework that considers architectural setups and benchmarksExplores the use of Carbon Nanotubes for power grid design

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Designing TSVs for 3D Integrated Circuits Nauman Khan, Soha Hassoun

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