Functional Verification of Dynamically Reconfigurable FPGA-based Systems

Provides researchers with an in-depth understanding of the challenges in verifying dynamically reconfigurable systems and the state-of-the-art methods used to overcome them Guides engineers with systematic approaches and tools to achieve verification closure in their dynamically reconfigurable projects Includes a comprehensive set of case studies, with an analysis of real bugs detected in the designs described Uses tools and techniques compatible with mainstream products (e.g. Xilinx/Altera tools, Model Sim simulator, Verilog/VHDL design language, etc. ...)

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