High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.

Verwandte Artikel

Weitere Produkte vom selben Autor

Download
ePUB
Download
PDF
Group-target Tracking Wen-dong Geng, Yuan-qin Wang, Zheng-hong Dong

93,08 €*
Language-driven Exploration and Implementation of Partially Re-configurable ASIPs Chattopadhyay, Anupam, Ascheid, Gerd, Meyr, Heinrich, Leupers, Rainer

160,49 €*
Energy Efficient High Performance Processors Haj-Yahya, Jawad, Chattopadhyay, Anupam, Ben Asher, Yosi, Mendelson, Avi

128,39 €*