Source-Synchronous Networks-On-Chip

Describes novel methods for high-speed network-on-chip (NoC) design Enables readers to understand NoC design from both circuit and architectural levels Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art Includes supplementary material: sn.pub/extras

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