Sustainable Wireless Network-on-Chip Architectures

Sustainable Wireless Network-on-Chip Architectures focuses on developing novel Dynamic Thermal Management (DTM) and Dynamic Voltage and Frequency Scaling (DVFS) algorithms that exploit the advantages inherent in WiNoC architectures. The methodologies proposed-combined with extensive experimental validation-collectively represent efforts to create a sustainable NoC architecture for future many-core chips. Current research trends show a necessary paradigm shift towards green and sustainable computing. As implementing massively parallel energy-efficient CPUs and reducing resource consumption become standard, and their speed and power continuously increase, energy issues become a significant concern. The need for promoting research in sustainable computing is imperative. As hundreds of cores are integrated in a single chip, designing effective packages for dissipating maximum heat is infeasible. Moreover, technology scaling is pushing the limits of affordable cooling, thereby requiring suitable design techniques to reduce peak temperatures. Addressing thermal concerns at different design stages is critical to the success of future generation systems. DTM and DVFS appear as solutions to avoid high spatial and temporal temperature variations among NoC components, and thereby mitigate local network hotspots. - Defines new complex, sustainable network-on-chip architectures to reduce network latency and energy - Develops topology-agnostic dynamic thermal management and dynamic voltage and frequency scaling techniques - Describes joint strategies for network- and core-level sustainability - Discusses novel algorithms that exploit the advantages inherent in Wireless Network-on-Chip architectures

Jacob A. Murray received his PhD in Electrical and Computer Engineering at the School of Electrical Engineering and Computer Science, Washington State University in 2014 and received his BS in Computer Engineering at Washington State University in 2010. He is a Clinical Assistant Professor and Program Coordinator at the School of Electrical Engineering and Computer Science, Washington State University, Everett. His current research interests include sustainable and low-power design for on-chip interconnection networks, routing for wireless on-chip communication networks, and temperature-aware design for topology-agnostic networks. He has been a Harold Frank Entrepreneur and participated as one of five undergraduate finalist teams in the 2010 National Collegiate Inventors Competition. He is a member of Tau Beta Pi, the national engineering honors society, and a member of the IEEE.