SystemVerilog for Verification
| Autor: | Chris Spear |
|---|---|
| EAN: | 9780387270388 |
| eBook Format: | |
| Sprache: | Englisch |
| Produktart: | eBook |
| Veröffentlichungsdatum: | 15.09.2006 |
| Untertitel: | A Guide to Learning the Testbench Language Features |
| Kategorie: | |
| Schlagworte: | Hardware Interface Software Spear SystemVerilog Verilog communication design methodology concepts programming testbenches testing verification |
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This book provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The authors explain methodology concepts for constructing testbenches that are modular and reusable. The text includes extensive coverage of the SystemVerilog 3.1a constructs, and reviews SystemVerilog 3.0 topics such as interfaces and data types. Included are detailed explanations of Object Oriented Programming and information on testbenches, multithreaded code, and interfacing to hardware designs.
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