Analysis and Design of Networks-on-Chip Under High Process Variation

Demonstrates the impact of process variation on Networks-on-Chip of different topologies Includes an overview of the synchronous clocking scheme, clock distribution network, main building blocks in asynchronous NoC design, handshake protocols, data encoding, asynchronous protocol converters and routing algorithms Describes a novel adaptive routing algorithm for asynchronous NoC designs, which selects the appropriate output path based on process variation and congestion Includes supplementary material: sn.pub/extras

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Analysis and Design of Networks-on-Chip Under High Process Variation Ezz-Eldin, Rabab, Hamed, Hesham F. A., El-Moursy, Magdy Ali

106,99 €*

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Analysis and Design of Networks-on-Chip Under High Process Variation Ezz-Eldin, Rabab, Hamed, Hesham F. A., El-Moursy, Magdy Ali

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