Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
| Autor: | Brandon Noia, Krishnendu Chakrabarty |
|---|---|
| EAN: | 9783319023786 |
| eBook Format: | |
| Sprache: | Englisch |
| Produktart: | eBook |
| Veröffentlichungsdatum: | 19.11.2013 |
| Kategorie: | |
| Schlagworte: | 3D Built-in Seft Test 3D IC Test 3D Integrated Circuit Design 3D Memory Test BIST for TSVs Through-Silicon Via |
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This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.
Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.
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