Testing of Interposer-Based 2.5D Integrated Circuits

Provides a single-source guide to the practical challenges in testing of 2.5D ICsPresents an efficient method to locate defects in a passive interposer before stackingDescribes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and delay faultsProvides a built-in self-test (BIST) architecture that can be enabled by the standard TAP controller in the IEEE 1149.1 standardDiscusses two ExTest scheduling strategies to implement interconnect testing between tiles inside an SoC dieIncludes a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICsIncludes supplementary material: sn.pub/extras

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