Testing of Interposer-Based 2.5D Integrated Circuits

Provides a single-source guide to the practical challenges in testing of 2.5D ICs Presents an efficient method to locate defects in a passive interposer before stacking Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and delay faults Provides a built-in self-test (BIST) architecture that can be enabled by the standard TAP controller in the IEEE 1149.1 standard Discusses two ExTest scheduling strategies to implement interconnect testing between tiles inside an SoC die Includes a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs Includes supplementary material: sn.pub/extras

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